This application claims the priority benefit of Taiwan application serial no. 89103560, filed Mar. 1, 2000.
1. Field of Invention
The present invention relates to the fabrication of semiconductor integrated circuits (ICs). More particularly, the present invention relates to a vernier for checking alignment accuracy (AA).
2. Description of Related Art
The fabrication of integrated circuits is accomplished by using different masks to perform photolithography and etching steps. In each step of photolithography, the present photomask must be aligned with a pattern already defined on the wafer by a previous photolithography operation. The alignment accuracy between a present IC pattern and a previous IC pattern becomes more and more important as the scale of the integrated circuits is reduced. In order to check the alignment accuracy, it is usual to design a vernier within scribe lines. The alignment check pattern of the vernier can be, for example, box-box, as illustrated in FIG. 1, or the pattern of bar-bar 200, as shown in FIG. 200.
To check the alignment accuracy, the peripheral alignment check pattern 102, 202 of the vernier 100, 200 is first exposed on the scribe line when the previous IC pattern is formed. Thereafter, when forming the present IC pattern, the central alignment check pattern 104, 204 of the vernier 100, 200, as shown in FIG. 1 and FIG. 2, is exposed within the peripheral alignment check pattern 102, 202 on the wafer. Accordingly, the alignment accuracy is checked by the distances X1, X2, Y1, Y2 between the peripheral alignment check pattern 102, 202 and the central alignment check pattern 104, 204 exposed on the wafer.
The width of the peripheral alignment check pattern 102, 202 and the central alignment check pattern 104, 204 of the vernier 100, 200 is usually about 2 xcexcm-4 xcexcm. However, the line width of ICs has been developed to approach to or even less then 0.25 xcexcm. In the photolithography of ICs, the line width of the photomask is equivalent to the slit that the exposure light passes. It is well known that the diffraction angle is in inverse proportion to the pitch of the slit   (            θ      ≈              λ        d              ,  
wherein xcex8 is diffraction angle, xcex is wavelength, and d is the pitch of the slit). Accordingly, the diffraction angle of the IC pattern is far larger than that of the alignment check pattern since the line width of the main pattern is less than that of the alignment check pattern. Such variance in diffraction angle causes difference of pattern distortion between the IC pattern and the alignment check pattern on the wafer when the exposure light passes the lens of the stepper. Therefore, the alignment accuracy checked by the alignment check pattern in this manner cannot accurately detect the alignment of the IC pattern.
The invention provides a multi-pitch vernier, thereby accurately checking the alignment accuracy of the IC patterns.
As embodied and broadly described herein, the invention provides a multi-pitch vernier including a plurality of pre-determined pattern elements with a constant pitch. The pitch, including a bright line and a dark line, equals to the design rule of the IC pattern. The width of the bright line can not be resolved by the exposure light. Accordingly, the multi-pitch vernier can check the alignment accuracy of the patterns formed by photolithography of IC.
This invention further provides a method of checking alignment accuracy using multi-pitch vernier. A peripheral alignment check pattern having multi-pitch is provided and a first pre-determined pattern of a peripheral alignment check pattern is formed. Thereafter, a second pre-determined pattern of a central alignment check pattern is formed using the central alignment check pattern. The distance between the peripheral and the central alignment check pattern is measured to check the alignment of the first and second pre-determined pattern. The peripheral and the central alignment check patterns comprise the patterns of box-box or bar-bar.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.